library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity acumuladorA is

Port (
		
		busdatosbaja: inout std_logic_vector (7 downto 0);
		busdatosalta: inout std_logic_vector (7 downto 0);
		A: out std_logic_vector (7 downto 0);
		
		--entradas
		clk : in STD_LOGIC;
	   --reset : in STD_LOGIC;
		WA : in std_logic; --senial de escritura 0 permite escritura y uno lectura
		EA : in std_logic_vector (1 downto 0); -- seleccion de bus de entrada (01 = Ai , 10 = Bi , 11 = Ci )
		
	
		--salida
		ACCAN : out std_logic;
		ACCAZ : out std_logic);
		
		
		-- registro interno
   	--dato   : buffer std_logic_vector (7 downto 0); --dato multiplexeado
		--salida  : buffer std_logic_vector (7 downto 0) -- contenido del registr		
end acumuladorA;

architecture Behavioral of acumuladorA is
	signal dato : std_logic_vector (7 downto 0);
begin
	process (clk, EA) begin
		if NOT ((EA(1) = '0') AND (EA(0) = '1')) then
			busdatosbaja	<=	"ZZZZZZZZ";
		elsif NOT ((EA(1) = '1') AND (EA(0) = '0')) then
			busdatosalta	<=	"ZZZZZZZZ";
		--elsif NOT ((ENA(1) = '1') AND (ENA(0) = '1')) then
			--C	<=	"ZZZZZZZZ";
    	elsif rising_edge (clk) then
			if WA = '1' then
				busdatosbaja		<=	dato;
				busdatosalta		<=	dato;
				A		<=	dato;
			else
				dato	<=	busdatosbaja OR busdatosalta;
			end if;
			ACCAZ		<= NOT (dato(7) AND dato(6) AND dato(5) AND dato(4) AND dato(3) AND dato(2) AND dato(1) AND dato(0));
			ACCAN		<= dato(7);
		end if;
		
  end process;
	
	
	
end Behavioral;